Today SystemC has become actually the standard language for describing behaviors VLSI. An international group of Open SystemC Initiative (OSCI) is engaged in its development and documentation.

SystemC language is based on C + + and due to the use of additional classes, provides new opportunities – the description of static and dynamic events, concurrency, account of temporal parameters, and also supports special types of data needed in the design of SoC . In principle, SystemC allows describing the system at the RTL, but it is the most effective and popular when dealing with behavioral models, first of all – at the transaction level.

In SystemC interchange of data (teams) between the individual blocks on the level of transaction is described simply. Interaction between modules occurs through calls of special functions (communication methods). Stable and regularly used a set of communication methods is called an interface. Component that implements an interface is called a channel. Two interacting modules connected to the channel through ports and exchange data through function calls declared in the interfaces and implemented by the appropriate channel.

There are two ways of interaction of software and executable models of equipment on SystemC. The first method is relevant when analyzing the architecture of future SoC as a whole, when it is very important to assess the load of tires and choose the right balance between hardware and software implemented features. Software is written (simulated) in C + + and run independently of the model of equipment, and communication with the TL-model SoC hardware is supported through communication ports. In this case all the time parameters of the equipment are specified in its SystemC-description.

Another way of co-simulation of software and hardware – is the implementation of software on the emulator of the processor integrated in the SystemC – the model of hte system of transactions level. Such integration is simple technically because usually emulators of cores are written in C / C + +. Then software is compiled and run on the emulator of the processor in the usual program-debugger. Only the speed of simulation increases in 100 times.

The concept of a virtual prototype is not realizable without an integrated environment of development, enabling:

• Use existing IP-blocks, regardless of language or level of abstraction of their description, and develop new IP-blocks;
• Collect a virtual prototype of the IP-blocks;
• Interact with a virtual prototype;
• Analyze the behavior of the system.

Furthermore, since SystemC is the standard language for describing system models, it is essential that the environment of Virtual Prototyping relieves developers to rewrite manually the draft system from SystemC on languages of description hardware (e.g., Verilog or VHDL).

All these tasks are successfully solved by IDE CoCentric System Studio of company Synopsys. System Studio – is an ideal area for the design hardware / software verification at the system level. It includes a simulation program in SystemC, which allows using SystemC-models of any origin at any level of abstraction. If necessary, at the level of transactions it can be easily connected RTL-models in Verilog / VHDL. The simulation programs on HDL from Synopsys – VCS and Sirocco are best for it.

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